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1 # HG changeset patch |
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2 # User Wolfgang Rosenauer <wr@rosenauer.org> |
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3 # Parent f805a250257be9c3ea570b34557150450e16dfec |
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4 |
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5 diff --git a/js/src/jit/GenerateAtomicOperations.py b/js/src/jit/GenerateAtomicOperations.py |
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6 --- a/js/src/jit/GenerateAtomicOperations.py |
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7 +++ b/js/src/jit/GenerateAtomicOperations.py |
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8 @@ -5,40 +5,41 @@ |
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9 # This script generates jit/AtomicOperationsGenerated.h |
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10 # |
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11 # See the big comment in jit/AtomicOperations.h for an explanation. |
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12 |
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13 import buildconfig |
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14 |
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15 is_64bit = "JS_64BIT" in buildconfig.defines |
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16 cpu_arch = buildconfig.substs["CPU_ARCH"] |
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17 +is_gcc = buildconfig.substs["CC_TYPE"] == "gcc" |
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18 |
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19 |
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20 def fmt_insn(s): |
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21 return '"' + s + '\\n\\t"\n' |
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22 |
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23 |
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24 def gen_seqcst(fun_name): |
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25 if cpu_arch in ("x86", "x86_64"): |
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26 return r""" |
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27 - inline void %(fun_name)s() { |
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28 + INLINE_ATTR void %(fun_name)s() { |
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29 asm volatile ("mfence\n\t" ::: "memory"); |
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30 }""" % { |
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31 "fun_name": fun_name, |
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32 } |
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33 if cpu_arch == "aarch64": |
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34 return r""" |
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35 - inline void %(fun_name)s() { |
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36 + INLINE_ATTR void %(fun_name)s() { |
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37 asm volatile ("dmb ish\n\t" ::: "memory"); |
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38 }""" % { |
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39 "fun_name": fun_name, |
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40 } |
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41 if cpu_arch == "arm": |
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42 return r""" |
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43 - inline void %(fun_name)s() { |
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44 + INLINE_ATTR void %(fun_name)s() { |
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45 asm volatile ("dmb sy\n\t" ::: "memory"); |
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46 }""" % { |
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47 "fun_name": fun_name, |
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48 } |
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49 raise Exception("Unexpected arch") |
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50 |
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51 |
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52 def gen_load(fun_name, cpp_type, size, barrier): |
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53 @@ -58,17 +59,17 @@ def gen_load(fun_name, cpp_type, size, b |
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54 elif size == 32: |
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55 insns += fmt_insn("movl (%[arg]), %[res]") |
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56 else: |
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57 assert size == 64 |
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58 insns += fmt_insn("movq (%[arg]), %[res]") |
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59 if barrier: |
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60 insns += fmt_insn("mfence") |
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61 return """ |
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62 - inline %(cpp_type)s %(fun_name)s(const %(cpp_type)s* arg) { |
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63 + INLINE_ATTR %(cpp_type)s %(fun_name)s(const %(cpp_type)s* arg) { |
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64 %(cpp_type)s res; |
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65 asm volatile (%(insns)s |
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66 : [res] "=r" (res) |
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67 : [arg] "r" (arg) |
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68 : "memory"); |
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69 return res; |
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70 }""" % { |
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71 "cpp_type": cpp_type, |
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72 @@ -86,17 +87,17 @@ def gen_load(fun_name, cpp_type, size, b |
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73 elif size == 32: |
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74 insns += fmt_insn("ldr %w[res], [%x[arg]]") |
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75 else: |
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76 assert size == 64 |
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77 insns += fmt_insn("ldr %x[res], [%x[arg]]") |
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78 if barrier: |
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79 insns += fmt_insn("dmb ish") |
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80 return """ |
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81 - inline %(cpp_type)s %(fun_name)s(const %(cpp_type)s* arg) { |
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82 + INLINE_ATTR %(cpp_type)s %(fun_name)s(const %(cpp_type)s* arg) { |
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83 %(cpp_type)s res; |
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84 asm volatile (%(insns)s |
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85 : [res] "=r" (res) |
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86 : [arg] "r" (arg) |
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87 : "memory"); |
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88 return res; |
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89 }""" % { |
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90 "cpp_type": cpp_type, |
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91 @@ -112,17 +113,17 @@ def gen_load(fun_name, cpp_type, size, b |
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92 elif size == 16: |
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93 insns += fmt_insn("ldrh %[res], [%[arg]]") |
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94 else: |
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95 assert size == 32 |
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96 insns += fmt_insn("ldr %[res], [%[arg]]") |
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97 if barrier: |
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98 insns += fmt_insn("dmb sy") |
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99 return """ |
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100 - inline %(cpp_type)s %(fun_name)s(const %(cpp_type)s* arg) { |
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101 + INLINE_ATTR %(cpp_type)s %(fun_name)s(const %(cpp_type)s* arg) { |
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102 %(cpp_type)s res; |
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103 asm volatile (%(insns)s |
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104 : [res] "=r" (res) |
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105 : [arg] "r" (arg) |
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106 : "memory"); |
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107 return res; |
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108 }""" % { |
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109 "cpp_type": cpp_type, |
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110 @@ -149,17 +150,17 @@ def gen_store(fun_name, cpp_type, size, |
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111 elif size == 32: |
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112 insns += fmt_insn("movl %[val], (%[addr])") |
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113 else: |
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114 assert size == 64 |
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115 insns += fmt_insn("movq %[val], (%[addr])") |
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116 if barrier: |
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117 insns += fmt_insn("mfence") |
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118 return """ |
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119 - inline void %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) { |
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120 + INLINE_ATTR void %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) { |
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121 asm volatile (%(insns)s |
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122 : |
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123 : [addr] "r" (addr), [val] "r"(val) |
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124 : "memory"); |
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125 }""" % { |
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126 "cpp_type": cpp_type, |
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127 "fun_name": fun_name, |
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128 "insns": insns, |
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129 @@ -175,17 +176,17 @@ def gen_store(fun_name, cpp_type, size, |
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130 elif size == 32: |
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131 insns += fmt_insn("str %w[val], [%x[addr]]") |
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132 else: |
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133 assert size == 64 |
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134 insns += fmt_insn("str %x[val], [%x[addr]]") |
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135 if barrier: |
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136 insns += fmt_insn("dmb ish") |
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137 return """ |
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138 - inline void %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) { |
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139 + INLINE_ATTR void %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) { |
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140 asm volatile (%(insns)s |
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141 : |
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142 : [addr] "r" (addr), [val] "r"(val) |
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143 : "memory"); |
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144 }""" % { |
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145 "cpp_type": cpp_type, |
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146 "fun_name": fun_name, |
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147 "insns": insns, |
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148 @@ -199,17 +200,17 @@ def gen_store(fun_name, cpp_type, size, |
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149 elif size == 16: |
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150 insns += fmt_insn("strh %[val], [%[addr]]") |
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151 else: |
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152 assert size == 32 |
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153 insns += fmt_insn("str %[val], [%[addr]]") |
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154 if barrier: |
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155 insns += fmt_insn("dmb sy") |
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156 return """ |
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157 - inline void %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) { |
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158 + INLINE_ATTR void %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) { |
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159 asm volatile (%(insns)s |
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160 : |
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161 : [addr] "r" (addr), [val] "r"(val) |
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162 : "memory"); |
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163 }""" % { |
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164 "cpp_type": cpp_type, |
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165 "fun_name": fun_name, |
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166 "insns": insns, |
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167 @@ -230,17 +231,17 @@ def gen_exchange(fun_name, cpp_type, siz |
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168 elif size == 16: |
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169 insns += fmt_insn("xchgw %[val], (%[addr])") |
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170 elif size == 32: |
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171 insns += fmt_insn("xchgl %[val], (%[addr])") |
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172 else: |
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173 assert size == 64 |
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174 insns += fmt_insn("xchgq %[val], (%[addr])") |
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175 return """ |
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176 - inline %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) { |
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177 + INLINE_ATTR %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) { |
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178 asm volatile (%(insns)s |
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179 : [val] "+r" (val) |
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180 : [addr] "r" (addr) |
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181 : "memory"); |
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182 return val; |
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183 }""" % { |
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184 "cpp_type": cpp_type, |
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185 "fun_name": fun_name, |
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186 @@ -261,17 +262,17 @@ def gen_exchange(fun_name, cpp_type, siz |
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187 insns += fmt_insn("stxr %w[scratch], %w[val], [%x[addr]]") |
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188 else: |
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189 assert size == 64 |
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190 insns += fmt_insn("ldxr %x[res], [%x[addr]]") |
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191 insns += fmt_insn("stxr %w[scratch], %x[val], [%x[addr]]") |
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192 insns += fmt_insn("cbnz %w[scratch], 0b") |
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193 insns += fmt_insn("dmb ish") |
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194 return """ |
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195 - inline %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) { |
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196 + INLINE_ATTR %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) { |
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197 %(cpp_type)s res; |
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198 uint32_t scratch; |
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199 asm volatile (%(insns)s |
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200 : [res] "=&r"(res), [scratch] "=&r"(scratch) |
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201 : [addr] "r" (addr), [val] "r"(val) |
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202 : "memory", "cc"); |
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203 return res; |
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204 }""" % { |
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205 @@ -292,17 +293,17 @@ def gen_exchange(fun_name, cpp_type, siz |
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206 else: |
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207 assert size == 32 |
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208 insns += fmt_insn("ldrex %[res], [%[addr]]") |
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209 insns += fmt_insn("strex %[scratch], %[val], [%[addr]]") |
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210 insns += fmt_insn("cmp %[scratch], #1") |
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211 insns += fmt_insn("beq 0b") |
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212 insns += fmt_insn("dmb sy") |
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213 return """ |
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214 - inline %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) { |
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215 + INLINE_ATTR %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) { |
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216 %(cpp_type)s res; |
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217 uint32_t scratch; |
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218 asm volatile (%(insns)s |
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219 : [res] "=&r"(res), [scratch] "=&r"(scratch) |
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220 : [addr] "r" (addr), [val] "r"(val) |
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221 : "memory", "cc"); |
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222 return res; |
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223 }""" % { |
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224 @@ -316,33 +317,33 @@ def gen_exchange(fun_name, cpp_type, siz |
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225 def gen_cmpxchg(fun_name, cpp_type, size): |
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226 # NOTE: the assembly code must match the generated code in: |
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227 # - MacroAssembler::compareExchange |
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228 # - MacroAssembler::compareExchange64 |
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229 if cpu_arch == "x86" and size == 64: |
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230 # Use a +A constraint to load `oldval` into EDX:EAX as input/output. |
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231 # `newval` is loaded into ECX:EBX. |
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232 return r""" |
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233 - inline %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr, |
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234 + INLINE_ATTR %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr, |
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235 %(cpp_type)s oldval, |
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236 %(cpp_type)s newval) { |
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237 asm volatile ("lock; cmpxchg8b (%%[addr])\n\t" |
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238 : "+A" (oldval) |
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239 : [addr] "r" (addr), |
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240 "b" (uint32_t(newval & 0xffff'ffff)), |
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241 "c" (uint32_t(newval >> 32)) |
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242 : "memory", "cc"); |
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243 return oldval; |
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244 }""" % { |
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245 "cpp_type": cpp_type, |
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246 "fun_name": fun_name, |
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247 } |
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248 if cpu_arch == "arm" and size == 64: |
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249 return r""" |
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250 - inline %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr, |
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251 + INLINE_ATTR %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr, |
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252 %(cpp_type)s oldval, |
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253 %(cpp_type)s newval) { |
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254 uint32_t oldval0 = oldval & 0xffff'ffff; |
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255 uint32_t oldval1 = oldval >> 32; |
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256 uint32_t newval0 = newval & 0xffff'ffff; |
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257 uint32_t newval1 = newval >> 32; |
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258 asm volatile ( |
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259 "dmb sy\n\t" |
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260 @@ -375,17 +376,17 @@ def gen_cmpxchg(fun_name, cpp_type, size |
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261 elif size == 16: |
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262 insns += fmt_insn("lock; cmpxchgw %[newval], (%[addr])") |
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263 elif size == 32: |
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264 insns += fmt_insn("lock; cmpxchgl %[newval], (%[addr])") |
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265 else: |
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266 assert size == 64 |
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267 insns += fmt_insn("lock; cmpxchgq %[newval], (%[addr])") |
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268 return """ |
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269 - inline %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr, |
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270 + INLINE_ATTR %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr, |
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271 %(cpp_type)s oldval, |
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272 %(cpp_type)s newval) { |
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273 asm volatile (%(insns)s |
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274 : [oldval] "+a" (oldval) |
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275 : [addr] "r" (addr), [newval] "r" (newval) |
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276 : "memory", "cc"); |
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277 return oldval; |
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278 }""" % { |
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279 @@ -420,17 +421,17 @@ def gen_cmpxchg(fun_name, cpp_type, size |
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280 insns += fmt_insn("mov %x[scratch], %x[oldval]") |
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281 insns += fmt_insn("ldxr %x[res], [%x[addr]]") |
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282 insns += fmt_insn("cmp %x[res], %x[scratch]") |
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283 insns += fmt_insn("b.ne 1f") |
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284 insns += fmt_insn("stxr %w[scratch], %x[newval], [%x[addr]]") |
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285 insns += fmt_insn("cbnz %w[scratch], 0b") |
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286 insns += fmt_insn("1: dmb ish") |
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287 return """ |
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288 - inline %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr, |
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289 + INLINE_ATTR %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr, |
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290 %(cpp_type)s oldval, |
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291 %(cpp_type)s newval) { |
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292 %(cpp_type)s res, scratch; |
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293 asm volatile (%(insns)s |
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294 : [res] "=&r" (res), [scratch] "=&r" (scratch) |
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295 : [addr] "r" (addr), [oldval] "r"(oldval), [newval] "r" (newval) |
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296 : "memory", "cc"); |
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297 return res; |
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298 @@ -461,17 +462,17 @@ def gen_cmpxchg(fun_name, cpp_type, size |
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299 insns += fmt_insn("ldrex %[res], [%[addr]]") |
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300 insns += fmt_insn("cmp %[res], %[scratch]") |
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301 insns += fmt_insn("bne 1f") |
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302 insns += fmt_insn("strex %[scratch], %[newval], [%[addr]]") |
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303 insns += fmt_insn("cmp %[scratch], #1") |
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304 insns += fmt_insn("beq 0b") |
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305 insns += fmt_insn("1: dmb sy") |
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306 return """ |
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307 - inline %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr, |
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308 + INLINE_ATTR %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr, |
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309 %(cpp_type)s oldval, |
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310 %(cpp_type)s newval) { |
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311 %(cpp_type)s res, scratch; |
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312 asm volatile (%(insns)s |
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313 : [res] "=&r" (res), [scratch] "=&r" (scratch) |
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314 : [addr] "r" (addr), [oldval] "r"(oldval), [newval] "r" (newval) |
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315 : "memory", "cc"); |
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316 return res; |
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317 @@ -496,17 +497,17 @@ def gen_fetchop(fun_name, cpp_type, size |
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318 elif size == 16: |
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319 insns += fmt_insn("lock; xaddw %[val], (%[addr])") |
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320 elif size == 32: |
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321 insns += fmt_insn("lock; xaddl %[val], (%[addr])") |
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322 else: |
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323 assert size == 64 |
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324 insns += fmt_insn("lock; xaddq %[val], (%[addr])") |
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325 return """ |
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326 - inline %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) { |
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327 + INLINE_ATTR %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) { |
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328 asm volatile (%(insns)s |
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329 : [val] "+&r" (val) |
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330 : [addr] "r" (addr) |
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331 : "memory", "cc"); |
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332 return val; |
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333 }""" % { |
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334 "cpp_type": cpp_type, |
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335 "fun_name": fun_name, |
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336 @@ -534,17 +535,17 @@ def gen_fetchop(fun_name, cpp_type, size |
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337 assert size == 64 |
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338 insns += fmt_insn("movq (%[addr]), %[res]") |
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339 insns += fmt_insn("0: movq %[res], %[scratch]") |
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340 insns += fmt_insn("OPq %[val], %[scratch]") |
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341 insns += fmt_insn("lock; cmpxchgq %[scratch], (%[addr])") |
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342 insns = insns.replace("OP", op) |
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343 insns += fmt_insn("jnz 0b") |
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344 return """ |
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345 - inline %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) { |
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346 + INLINE_ATTR %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) { |
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347 %(cpp_type)s res, scratch; |
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348 asm volatile (%(insns)s |
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349 : [res] "=&a" (res), [scratch] "=&r" (scratch) |
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350 : [addr] "r" (addr), [val] "r"(val) |
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351 : "memory", "cc"); |
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352 return res; |
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353 }""" % { |
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354 "cpp_type": cpp_type, |
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355 @@ -576,17 +577,17 @@ def gen_fetchop(fun_name, cpp_type, size |
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356 if cpu_op == "or": |
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357 cpu_op = "orr" |
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358 if cpu_op == "xor": |
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359 cpu_op = "eor" |
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360 insns = insns.replace("OP", cpu_op) |
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361 insns += fmt_insn("cbnz %w[scratch2], 0b") |
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362 insns += fmt_insn("dmb ish") |
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363 return """ |
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364 - inline %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) { |
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365 + INLINE_ATTR %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) { |
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366 %(cpp_type)s res; |
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367 uintptr_t scratch1, scratch2; |
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368 asm volatile (%(insns)s |
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369 : [res] "=&r" (res), [scratch1] "=&r" (scratch1), [scratch2] "=&r"(scratch2) |
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370 : [addr] "r" (addr), [val] "r"(val) |
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371 : "memory", "cc"); |
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372 return res; |
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373 }""" % { |
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374 @@ -616,17 +617,17 @@ def gen_fetchop(fun_name, cpp_type, size |
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375 cpu_op = "orr" |
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376 if cpu_op == "xor": |
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377 cpu_op = "eor" |
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378 insns = insns.replace("OP", cpu_op) |
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379 insns += fmt_insn("cmp %[scratch2], #1") |
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380 insns += fmt_insn("beq 0b") |
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381 insns += fmt_insn("dmb sy") |
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382 return """ |
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383 - inline %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) { |
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384 + INLINE_ATTR %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) { |
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385 %(cpp_type)s res; |
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386 uintptr_t scratch1, scratch2; |
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387 asm volatile (%(insns)s |
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388 : [res] "=&r" (res), [scratch1] "=&r" (scratch1), [scratch2] "=&r"(scratch2) |
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389 : [addr] "r" (addr), [val] "r"(val) |
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390 : "memory", "cc"); |
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391 return res; |
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392 }""" % { |
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393 @@ -660,33 +661,33 @@ def gen_copy(fun_name, cpp_type, size, u |
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394 insns += fmt_insn("ldrb %w[scratch], [%x[src], OFFSET]") |
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395 insns += fmt_insn("strb %w[scratch], [%x[dst], OFFSET]") |
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396 else: |
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397 assert size == 8 |
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398 insns += fmt_insn("ldr %x[scratch], [%x[src], OFFSET]") |
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399 insns += fmt_insn("str %x[scratch], [%x[dst], OFFSET]") |
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400 elif cpu_arch == "arm": |
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401 if size == 1: |
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402 - insns += fmt_insn("ldrb %[scratch], [%[src], OFFSET]") |
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403 - insns += fmt_insn("strb %[scratch], [%[dst], OFFSET]") |
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404 + insns += fmt_insn("ldrb %[scratch], [%[src], #OFFSET]") |
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405 + insns += fmt_insn("strb %[scratch], [%[dst], #OFFSET]") |
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406 else: |
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407 assert size == 4 |
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408 - insns += fmt_insn("ldr %[scratch], [%[src], OFFSET]") |
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409 - insns += fmt_insn("str %[scratch], [%[dst], OFFSET]") |
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410 + insns += fmt_insn("ldr %[scratch], [%[src], #OFFSET]") |
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411 + insns += fmt_insn("str %[scratch], [%[dst], #OFFSET]") |
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412 else: |
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413 raise Exception("Unexpected arch") |
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414 insns = insns.replace("OFFSET", str(offset * size)) |
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415 |
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416 if direction == "down": |
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417 offset += 1 |
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418 else: |
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419 offset -= 1 |
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420 |
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421 return """ |
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422 - inline void %(fun_name)s(uint8_t* dst, const uint8_t* src) { |
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423 + INLINE_ATTR void %(fun_name)s(uint8_t* dst, const uint8_t* src) { |
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424 %(cpp_type)s* dst_ = reinterpret_cast<%(cpp_type)s*>(dst); |
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425 const %(cpp_type)s* src_ = reinterpret_cast<const %(cpp_type)s*>(src); |
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426 %(cpp_type)s scratch; |
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427 asm volatile (%(insns)s |
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428 : [scratch] "=&r" (scratch) |
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429 : [dst] "r" (dst_), [src] "r"(src_) |
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430 : "memory"); |
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431 }""" % { |
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432 @@ -848,14 +849,21 @@ def generate_atomics_header(c_out): |
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433 "constexpr size_t JS_GENERATED_ATOMICS_BLOCKSIZE = " |
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434 + str(blocksize) |
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435 + ";\n" |
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436 ) |
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437 contents += ( |
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438 "constexpr size_t JS_GENERATED_ATOMICS_WORDSIZE = " + str(wordsize) + ";\n" |
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439 ) |
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440 |
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441 + # Work around a GCC issue on 32-bit x86 by adding MOZ_NEVER_INLINE. |
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442 + # See bug 1756347. |
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443 + if is_gcc and cpu_arch == "x86": |
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444 + contents = contents.replace("INLINE_ATTR", "MOZ_NEVER_INLINE inline") |
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445 + else: |
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446 + contents = contents.replace("INLINE_ATTR", "inline") |
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447 + |
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448 c_out.write( |
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449 HEADER_TEMPLATE |
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450 % { |
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451 "contents": contents, |
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452 } |
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453 ) |