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1172
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# HG changeset patch
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# User Wolfgang Rosenauer <wr@rosenauer.org>
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# Parent f805a250257be9c3ea570b34557150450e16dfec
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diff --git a/js/src/jit/GenerateAtomicOperations.py b/js/src/jit/GenerateAtomicOperations.py
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--- a/js/src/jit/GenerateAtomicOperations.py
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+++ b/js/src/jit/GenerateAtomicOperations.py
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@@ -5,40 +5,41 @@
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# This script generates jit/AtomicOperationsGenerated.h
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#
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# See the big comment in jit/AtomicOperations.h for an explanation.
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import buildconfig
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is_64bit = "JS_64BIT" in buildconfig.defines
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cpu_arch = buildconfig.substs["CPU_ARCH"]
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+is_gcc = buildconfig.substs["CC_TYPE"] == "gcc"
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def fmt_insn(s):
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return '"' + s + '\\n\\t"\n'
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def gen_seqcst(fun_name):
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if cpu_arch in ("x86", "x86_64"):
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return r"""
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- inline void %(fun_name)s() {
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+ INLINE_ATTR void %(fun_name)s() {
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asm volatile ("mfence\n\t" ::: "memory");
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}""" % {
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"fun_name": fun_name,
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}
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if cpu_arch == "aarch64":
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return r"""
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- inline void %(fun_name)s() {
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+ INLINE_ATTR void %(fun_name)s() {
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asm volatile ("dmb ish\n\t" ::: "memory");
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}""" % {
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"fun_name": fun_name,
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}
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if cpu_arch == "arm":
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return r"""
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- inline void %(fun_name)s() {
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+ INLINE_ATTR void %(fun_name)s() {
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asm volatile ("dmb sy\n\t" ::: "memory");
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}""" % {
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"fun_name": fun_name,
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}
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raise Exception("Unexpected arch")
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def gen_load(fun_name, cpp_type, size, barrier):
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@@ -58,17 +59,17 @@ def gen_load(fun_name, cpp_type, size, b
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elif size == 32:
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insns += fmt_insn("movl (%[arg]), %[res]")
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else:
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assert size == 64
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insns += fmt_insn("movq (%[arg]), %[res]")
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if barrier:
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insns += fmt_insn("mfence")
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return """
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- inline %(cpp_type)s %(fun_name)s(const %(cpp_type)s* arg) {
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+ INLINE_ATTR %(cpp_type)s %(fun_name)s(const %(cpp_type)s* arg) {
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%(cpp_type)s res;
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asm volatile (%(insns)s
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: [res] "=r" (res)
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: [arg] "r" (arg)
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: "memory");
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return res;
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}""" % {
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"cpp_type": cpp_type,
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@@ -86,17 +87,17 @@ def gen_load(fun_name, cpp_type, size, b
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elif size == 32:
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insns += fmt_insn("ldr %w[res], [%x[arg]]")
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else:
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assert size == 64
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insns += fmt_insn("ldr %x[res], [%x[arg]]")
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if barrier:
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insns += fmt_insn("dmb ish")
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return """
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- inline %(cpp_type)s %(fun_name)s(const %(cpp_type)s* arg) {
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+ INLINE_ATTR %(cpp_type)s %(fun_name)s(const %(cpp_type)s* arg) {
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%(cpp_type)s res;
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asm volatile (%(insns)s
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: [res] "=r" (res)
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: [arg] "r" (arg)
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: "memory");
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return res;
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}""" % {
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"cpp_type": cpp_type,
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@@ -112,17 +113,17 @@ def gen_load(fun_name, cpp_type, size, b
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elif size == 16:
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insns += fmt_insn("ldrh %[res], [%[arg]]")
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else:
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assert size == 32
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insns += fmt_insn("ldr %[res], [%[arg]]")
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if barrier:
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insns += fmt_insn("dmb sy")
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return """
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- inline %(cpp_type)s %(fun_name)s(const %(cpp_type)s* arg) {
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+ INLINE_ATTR %(cpp_type)s %(fun_name)s(const %(cpp_type)s* arg) {
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%(cpp_type)s res;
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asm volatile (%(insns)s
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: [res] "=r" (res)
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: [arg] "r" (arg)
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: "memory");
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return res;
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}""" % {
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"cpp_type": cpp_type,
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@@ -149,17 +150,17 @@ def gen_store(fun_name, cpp_type, size,
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elif size == 32:
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insns += fmt_insn("movl %[val], (%[addr])")
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else:
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assert size == 64
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insns += fmt_insn("movq %[val], (%[addr])")
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if barrier:
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insns += fmt_insn("mfence")
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return """
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- inline void %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) {
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+ INLINE_ATTR void %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) {
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asm volatile (%(insns)s
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:
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: [addr] "r" (addr), [val] "r"(val)
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: "memory");
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}""" % {
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"cpp_type": cpp_type,
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"fun_name": fun_name,
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"insns": insns,
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@@ -175,17 +176,17 @@ def gen_store(fun_name, cpp_type, size,
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elif size == 32:
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insns += fmt_insn("str %w[val], [%x[addr]]")
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else:
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assert size == 64
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insns += fmt_insn("str %x[val], [%x[addr]]")
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if barrier:
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insns += fmt_insn("dmb ish")
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return """
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- inline void %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) {
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+ INLINE_ATTR void %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) {
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asm volatile (%(insns)s
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:
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: [addr] "r" (addr), [val] "r"(val)
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: "memory");
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}""" % {
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"cpp_type": cpp_type,
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"fun_name": fun_name,
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"insns": insns,
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@@ -199,17 +200,17 @@ def gen_store(fun_name, cpp_type, size,
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elif size == 16:
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insns += fmt_insn("strh %[val], [%[addr]]")
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else:
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assert size == 32
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insns += fmt_insn("str %[val], [%[addr]]")
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if barrier:
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insns += fmt_insn("dmb sy")
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return """
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- inline void %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) {
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+ INLINE_ATTR void %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) {
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asm volatile (%(insns)s
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:
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: [addr] "r" (addr), [val] "r"(val)
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: "memory");
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}""" % {
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"cpp_type": cpp_type,
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"fun_name": fun_name,
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"insns": insns,
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@@ -230,17 +231,17 @@ def gen_exchange(fun_name, cpp_type, siz
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elif size == 16:
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insns += fmt_insn("xchgw %[val], (%[addr])")
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elif size == 32:
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insns += fmt_insn("xchgl %[val], (%[addr])")
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else:
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assert size == 64
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insns += fmt_insn("xchgq %[val], (%[addr])")
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return """
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- inline %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) {
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+ INLINE_ATTR %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) {
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asm volatile (%(insns)s
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: [val] "+r" (val)
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: [addr] "r" (addr)
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: "memory");
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return val;
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}""" % {
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"cpp_type": cpp_type,
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"fun_name": fun_name,
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@@ -261,17 +262,17 @@ def gen_exchange(fun_name, cpp_type, siz
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insns += fmt_insn("stxr %w[scratch], %w[val], [%x[addr]]")
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else:
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assert size == 64
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insns += fmt_insn("ldxr %x[res], [%x[addr]]")
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insns += fmt_insn("stxr %w[scratch], %x[val], [%x[addr]]")
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insns += fmt_insn("cbnz %w[scratch], 0b")
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insns += fmt_insn("dmb ish")
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return """
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- inline %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) {
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+ INLINE_ATTR %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) {
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%(cpp_type)s res;
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uint32_t scratch;
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asm volatile (%(insns)s
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: [res] "=&r"(res), [scratch] "=&r"(scratch)
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: [addr] "r" (addr), [val] "r"(val)
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: "memory", "cc");
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return res;
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}""" % {
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@@ -292,17 +293,17 @@ def gen_exchange(fun_name, cpp_type, siz
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else:
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assert size == 32
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insns += fmt_insn("ldrex %[res], [%[addr]]")
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insns += fmt_insn("strex %[scratch], %[val], [%[addr]]")
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insns += fmt_insn("cmp %[scratch], #1")
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insns += fmt_insn("beq 0b")
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insns += fmt_insn("dmb sy")
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return """
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- inline %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) {
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+ INLINE_ATTR %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) {
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%(cpp_type)s res;
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uint32_t scratch;
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asm volatile (%(insns)s
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: [res] "=&r"(res), [scratch] "=&r"(scratch)
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: [addr] "r" (addr), [val] "r"(val)
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: "memory", "cc");
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return res;
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}""" % {
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@@ -316,33 +317,33 @@ def gen_exchange(fun_name, cpp_type, siz
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def gen_cmpxchg(fun_name, cpp_type, size):
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# NOTE: the assembly code must match the generated code in:
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# - MacroAssembler::compareExchange
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# - MacroAssembler::compareExchange64
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if cpu_arch == "x86" and size == 64:
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# Use a +A constraint to load `oldval` into EDX:EAX as input/output.
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# `newval` is loaded into ECX:EBX.
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return r"""
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- inline %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr,
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+ INLINE_ATTR %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr,
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%(cpp_type)s oldval,
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%(cpp_type)s newval) {
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asm volatile ("lock; cmpxchg8b (%%[addr])\n\t"
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: "+A" (oldval)
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: [addr] "r" (addr),
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"b" (uint32_t(newval & 0xffff'ffff)),
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"c" (uint32_t(newval >> 32))
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: "memory", "cc");
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return oldval;
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}""" % {
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"cpp_type": cpp_type,
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"fun_name": fun_name,
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}
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if cpu_arch == "arm" and size == 64:
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return r"""
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- inline %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr,
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+ INLINE_ATTR %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr,
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%(cpp_type)s oldval,
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%(cpp_type)s newval) {
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uint32_t oldval0 = oldval & 0xffff'ffff;
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uint32_t oldval1 = oldval >> 32;
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uint32_t newval0 = newval & 0xffff'ffff;
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uint32_t newval1 = newval >> 32;
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asm volatile (
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"dmb sy\n\t"
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@@ -375,17 +376,17 @@ def gen_cmpxchg(fun_name, cpp_type, size
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elif size == 16:
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insns += fmt_insn("lock; cmpxchgw %[newval], (%[addr])")
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elif size == 32:
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insns += fmt_insn("lock; cmpxchgl %[newval], (%[addr])")
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else:
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assert size == 64
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insns += fmt_insn("lock; cmpxchgq %[newval], (%[addr])")
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return """
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- inline %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr,
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+ INLINE_ATTR %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr,
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%(cpp_type)s oldval,
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%(cpp_type)s newval) {
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asm volatile (%(insns)s
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: [oldval] "+a" (oldval)
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: [addr] "r" (addr), [newval] "r" (newval)
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: "memory", "cc");
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return oldval;
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}""" % {
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@@ -420,17 +421,17 @@ def gen_cmpxchg(fun_name, cpp_type, size
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insns += fmt_insn("mov %x[scratch], %x[oldval]")
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insns += fmt_insn("ldxr %x[res], [%x[addr]]")
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insns += fmt_insn("cmp %x[res], %x[scratch]")
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insns += fmt_insn("b.ne 1f")
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insns += fmt_insn("stxr %w[scratch], %x[newval], [%x[addr]]")
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insns += fmt_insn("cbnz %w[scratch], 0b")
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insns += fmt_insn("1: dmb ish")
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return """
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- inline %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr,
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+ INLINE_ATTR %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr,
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%(cpp_type)s oldval,
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%(cpp_type)s newval) {
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%(cpp_type)s res, scratch;
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asm volatile (%(insns)s
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: [res] "=&r" (res), [scratch] "=&r" (scratch)
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: [addr] "r" (addr), [oldval] "r"(oldval), [newval] "r" (newval)
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: "memory", "cc");
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297 |
return res;
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298 |
@@ -461,17 +462,17 @@ def gen_cmpxchg(fun_name, cpp_type, size
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299 |
insns += fmt_insn("ldrex %[res], [%[addr]]")
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300 |
insns += fmt_insn("cmp %[res], %[scratch]")
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301 |
insns += fmt_insn("bne 1f")
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302 |
insns += fmt_insn("strex %[scratch], %[newval], [%[addr]]")
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303 |
insns += fmt_insn("cmp %[scratch], #1")
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|
|
304 |
insns += fmt_insn("beq 0b")
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|
305 |
insns += fmt_insn("1: dmb sy")
|
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|
306 |
return """
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|
|
307 |
- inline %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr,
|
|
|
308 |
+ INLINE_ATTR %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr,
|
|
|
309 |
%(cpp_type)s oldval,
|
|
|
310 |
%(cpp_type)s newval) {
|
|
|
311 |
%(cpp_type)s res, scratch;
|
|
|
312 |
asm volatile (%(insns)s
|
|
|
313 |
: [res] "=&r" (res), [scratch] "=&r" (scratch)
|
|
|
314 |
: [addr] "r" (addr), [oldval] "r"(oldval), [newval] "r" (newval)
|
|
|
315 |
: "memory", "cc");
|
|
|
316 |
return res;
|
|
|
317 |
@@ -496,17 +497,17 @@ def gen_fetchop(fun_name, cpp_type, size
|
|
|
318 |
elif size == 16:
|
|
|
319 |
insns += fmt_insn("lock; xaddw %[val], (%[addr])")
|
|
|
320 |
elif size == 32:
|
|
|
321 |
insns += fmt_insn("lock; xaddl %[val], (%[addr])")
|
|
|
322 |
else:
|
|
|
323 |
assert size == 64
|
|
|
324 |
insns += fmt_insn("lock; xaddq %[val], (%[addr])")
|
|
|
325 |
return """
|
|
|
326 |
- inline %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) {
|
|
|
327 |
+ INLINE_ATTR %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) {
|
|
|
328 |
asm volatile (%(insns)s
|
|
|
329 |
: [val] "+&r" (val)
|
|
|
330 |
: [addr] "r" (addr)
|
|
|
331 |
: "memory", "cc");
|
|
|
332 |
return val;
|
|
|
333 |
}""" % {
|
|
|
334 |
"cpp_type": cpp_type,
|
|
|
335 |
"fun_name": fun_name,
|
|
|
336 |
@@ -534,17 +535,17 @@ def gen_fetchop(fun_name, cpp_type, size
|
|
|
337 |
assert size == 64
|
|
|
338 |
insns += fmt_insn("movq (%[addr]), %[res]")
|
|
|
339 |
insns += fmt_insn("0: movq %[res], %[scratch]")
|
|
|
340 |
insns += fmt_insn("OPq %[val], %[scratch]")
|
|
|
341 |
insns += fmt_insn("lock; cmpxchgq %[scratch], (%[addr])")
|
|
|
342 |
insns = insns.replace("OP", op)
|
|
|
343 |
insns += fmt_insn("jnz 0b")
|
|
|
344 |
return """
|
|
|
345 |
- inline %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) {
|
|
|
346 |
+ INLINE_ATTR %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) {
|
|
|
347 |
%(cpp_type)s res, scratch;
|
|
|
348 |
asm volatile (%(insns)s
|
|
|
349 |
: [res] "=&a" (res), [scratch] "=&r" (scratch)
|
|
|
350 |
: [addr] "r" (addr), [val] "r"(val)
|
|
|
351 |
: "memory", "cc");
|
|
|
352 |
return res;
|
|
|
353 |
}""" % {
|
|
|
354 |
"cpp_type": cpp_type,
|
|
|
355 |
@@ -576,17 +577,17 @@ def gen_fetchop(fun_name, cpp_type, size
|
|
|
356 |
if cpu_op == "or":
|
|
|
357 |
cpu_op = "orr"
|
|
|
358 |
if cpu_op == "xor":
|
|
|
359 |
cpu_op = "eor"
|
|
|
360 |
insns = insns.replace("OP", cpu_op)
|
|
|
361 |
insns += fmt_insn("cbnz %w[scratch2], 0b")
|
|
|
362 |
insns += fmt_insn("dmb ish")
|
|
|
363 |
return """
|
|
|
364 |
- inline %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) {
|
|
|
365 |
+ INLINE_ATTR %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) {
|
|
|
366 |
%(cpp_type)s res;
|
|
|
367 |
uintptr_t scratch1, scratch2;
|
|
|
368 |
asm volatile (%(insns)s
|
|
|
369 |
: [res] "=&r" (res), [scratch1] "=&r" (scratch1), [scratch2] "=&r"(scratch2)
|
|
|
370 |
: [addr] "r" (addr), [val] "r"(val)
|
|
|
371 |
: "memory", "cc");
|
|
|
372 |
return res;
|
|
|
373 |
}""" % {
|
|
|
374 |
@@ -616,17 +617,17 @@ def gen_fetchop(fun_name, cpp_type, size
|
|
|
375 |
cpu_op = "orr"
|
|
|
376 |
if cpu_op == "xor":
|
|
|
377 |
cpu_op = "eor"
|
|
|
378 |
insns = insns.replace("OP", cpu_op)
|
|
|
379 |
insns += fmt_insn("cmp %[scratch2], #1")
|
|
|
380 |
insns += fmt_insn("beq 0b")
|
|
|
381 |
insns += fmt_insn("dmb sy")
|
|
|
382 |
return """
|
|
|
383 |
- inline %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) {
|
|
|
384 |
+ INLINE_ATTR %(cpp_type)s %(fun_name)s(%(cpp_type)s* addr, %(cpp_type)s val) {
|
|
|
385 |
%(cpp_type)s res;
|
|
|
386 |
uintptr_t scratch1, scratch2;
|
|
|
387 |
asm volatile (%(insns)s
|
|
|
388 |
: [res] "=&r" (res), [scratch1] "=&r" (scratch1), [scratch2] "=&r"(scratch2)
|
|
|
389 |
: [addr] "r" (addr), [val] "r"(val)
|
|
|
390 |
: "memory", "cc");
|
|
|
391 |
return res;
|
|
|
392 |
}""" % {
|
|
|
393 |
@@ -660,33 +661,33 @@ def gen_copy(fun_name, cpp_type, size, u
|
|
|
394 |
insns += fmt_insn("ldrb %w[scratch], [%x[src], OFFSET]")
|
|
|
395 |
insns += fmt_insn("strb %w[scratch], [%x[dst], OFFSET]")
|
|
|
396 |
else:
|
|
|
397 |
assert size == 8
|
|
|
398 |
insns += fmt_insn("ldr %x[scratch], [%x[src], OFFSET]")
|
|
|
399 |
insns += fmt_insn("str %x[scratch], [%x[dst], OFFSET]")
|
|
|
400 |
elif cpu_arch == "arm":
|
|
|
401 |
if size == 1:
|
|
|
402 |
- insns += fmt_insn("ldrb %[scratch], [%[src], OFFSET]")
|
|
|
403 |
- insns += fmt_insn("strb %[scratch], [%[dst], OFFSET]")
|
|
|
404 |
+ insns += fmt_insn("ldrb %[scratch], [%[src], #OFFSET]")
|
|
|
405 |
+ insns += fmt_insn("strb %[scratch], [%[dst], #OFFSET]")
|
|
|
406 |
else:
|
|
|
407 |
assert size == 4
|
|
|
408 |
- insns += fmt_insn("ldr %[scratch], [%[src], OFFSET]")
|
|
|
409 |
- insns += fmt_insn("str %[scratch], [%[dst], OFFSET]")
|
|
|
410 |
+ insns += fmt_insn("ldr %[scratch], [%[src], #OFFSET]")
|
|
|
411 |
+ insns += fmt_insn("str %[scratch], [%[dst], #OFFSET]")
|
|
|
412 |
else:
|
|
|
413 |
raise Exception("Unexpected arch")
|
|
|
414 |
insns = insns.replace("OFFSET", str(offset * size))
|
|
|
415 |
|
|
|
416 |
if direction == "down":
|
|
|
417 |
offset += 1
|
|
|
418 |
else:
|
|
|
419 |
offset -= 1
|
|
|
420 |
|
|
|
421 |
return """
|
|
|
422 |
- inline void %(fun_name)s(uint8_t* dst, const uint8_t* src) {
|
|
|
423 |
+ INLINE_ATTR void %(fun_name)s(uint8_t* dst, const uint8_t* src) {
|
|
|
424 |
%(cpp_type)s* dst_ = reinterpret_cast<%(cpp_type)s*>(dst);
|
|
|
425 |
const %(cpp_type)s* src_ = reinterpret_cast<const %(cpp_type)s*>(src);
|
|
|
426 |
%(cpp_type)s scratch;
|
|
|
427 |
asm volatile (%(insns)s
|
|
|
428 |
: [scratch] "=&r" (scratch)
|
|
|
429 |
: [dst] "r" (dst_), [src] "r"(src_)
|
|
|
430 |
: "memory");
|
|
|
431 |
}""" % {
|
|
|
432 |
@@ -848,14 +849,21 @@ def generate_atomics_header(c_out):
|
|
|
433 |
"constexpr size_t JS_GENERATED_ATOMICS_BLOCKSIZE = "
|
|
|
434 |
+ str(blocksize)
|
|
|
435 |
+ ";\n"
|
|
|
436 |
)
|
|
|
437 |
contents += (
|
|
|
438 |
"constexpr size_t JS_GENERATED_ATOMICS_WORDSIZE = " + str(wordsize) + ";\n"
|
|
|
439 |
)
|
|
|
440 |
|
|
|
441 |
+ # Work around a GCC issue on 32-bit x86 by adding MOZ_NEVER_INLINE.
|
|
|
442 |
+ # See bug 1756347.
|
|
|
443 |
+ if is_gcc and cpu_arch == "x86":
|
|
|
444 |
+ contents = contents.replace("INLINE_ATTR", "MOZ_NEVER_INLINE inline")
|
|
|
445 |
+ else:
|
|
|
446 |
+ contents = contents.replace("INLINE_ATTR", "inline")
|
|
|
447 |
+
|
|
|
448 |
c_out.write(
|
|
|
449 |
HEADER_TEMPLATE
|
|
|
450 |
% {
|
|
|
451 |
"contents": contents,
|
|
|
452 |
}
|
|
|
453 |
)
|